View SPFMIR302_41225.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SPF MIR3 02
SPF MIR3 02
Plastic Fiber Optic Receiver including Bigfoot
Preliminary Data Sheet
TM
IC for MOST
(R)
The data sheet of the 4-pin MOST Optical Receiver (MIR3 02) has to be taken as preliminary. Samples which are delivered before the qualification and the production release are engineering samples.
Features
Excellent solution for converting high speed data from Plastic Optical Fiber (POF) to digital output. * * * * * * High speed receiver up to 50 MBaud (25Mbit/s net data rate) TTL Data Output (Light to Logic Function) Network activity sensing during ZeroPower Mode (ICC<10A) BUS Activity Status Output Good 650nm sensitivity for working in a low attenuation range of PMMA Fiber Low cost
Description
The 4-pin MOST Optical Receiver (MIR3 02) is a TM highly integrated CMOS IC (Bigfoot ) combined with a high speed PIN - diode designed to receive up to 25Mbit/s optical data which is bi-phase coded at up to 50Mbaud and convert this optical data to a TTL compatible data stream. This high performance, low cost, CMOS receiver consists of a low noise transimpedance amplifier and comparator in the data path. A timer circuit puts the part into a low power mode if optical data is not received for 10s (typ.). During the low power mode, the PIN diode is still being observed and if activity is detected, Bigfoot will resume full power operation within 3.5ms (typ.). A STATUS-pin indicates if modulated light is received (Light on -> STATUS = low). With the STATUS-pin the power supply of the whole MOST device can be switched ON.
Applications
* Optical Receiver for MOST Systems
SPF MOR 003 SPF MIR3 02
Bigfoot Receiver
Amplification/Data Slicing/Pulse Width Correction
5: Vcc
8: RX_DATA
6: GND
Activity Detection
7: STATUS
Actual design status: Bigfoot IC Revision J package type Optical Sensitivity device marking Data sheet is valid since 2-Dec-02
CAI
-24.5 dBm
date code, MIR3 02
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 1
SPF MIR3 02
Maximum Ratings
Parameter Storage Temperature Range Junction Temperature Soldering Temperature (>2.5 mm from case bottom t5s) Power Dissipation Power Supply Voltage DC Current To Any Pin Except Power Symbol TSTG TJ TS PTOT VCCMax II/OMax Min -40 -40 -0.5 Max 100 100 235 300 6.0 10 Unit C C C mW V mA
Recommended Operating Conditions
Parameter Supply Voltage Operating Temperature Range Symbol VCC TA Min 4.75 -40 Max 5.25 85 Unit V C
All the data in this specification refers to the operating conditions above, unless otherwise stated.
Optical Signal Characteristics (22.5 MBit MOST Data)
Parameter Maximum Photosensitivity Wavelength (TA=25C) Photosensitivity Spectral Range (TA=25C) (S 10% Smax) Optical Sensitivity Optical overload *1) *2) *3) *1) *2) *3) Symbol Smax S Pmax POFF Min 400 -24.5 -2 Typ 850 Max 1100 -40 Unit nm nm dBm dBm dBm
Optical receivable power for low power mode *1)
*1) Optical power data are average values when using a MOST optical transmitter with peak of 650 nm typical and measured at the end of a plastic optical fiber with metal insert. *2) It is proposed to use the OptoLyzer4MOST, MOST Optical Network Analyzer, described in: http://www.oasis.de (with MOST Data @44.1KHz FS) or Standard BER Measuring Equipment -9 7 running with 45 MBaud (BER 10 with 2 -1 word length). *3) The values are determined by locking a OS8104 in Slave-mode to the signal.
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 2
SPF MIR3 02
DC Characteristics
Parameter Supply Voltage Low Level Output Voltage High Level Output Voltage Supply Current Test Conditions IOL = 2.4mA IOH = 2.4mA Full power mode Low power mode Symbol VCC VOL VOH ICC Min 4.75 VCC-1.0 Typ 5.0 18.5 5 Max 5.25 0.4 22 10 Unit V V V mA A
AC Electrical Characteristics
Parameter Power Supply Rejection Ratio Output Rise Time Output Fall Time Output Pulse Width Variation *2) Output Average Pulse Width Distortion *2) Power-up time at detection of rising VCC Power-up time from low power mode *3) Low Power mode timer delay Test Conditions 25 MHz Power Supply Noise CL=10pF *1) CL=10pF *1) MOST Data 44.1 kHz FS (-2...-24.5dBm) MOST Data 44.1 kHz FS (-2...-24.5dBm) When part first powers up Time from detection of inactivity to low power mode Symbol PSRR tr tf tPWV tAPWD tPUO tPU TLPM Min 15.5 0 Typ 30 7.5 6 3.5 2.5 10 Max 9 7 32.8 8 17 12 22 Unit dB ns ns ns ns ms ms s
*1) With CL = 25pF, the rise/ fall increases to about 12 ns. Therefore, keep the distance from Bigfoot to the MOST - chip as short as possible for keeping CL low. *2) MOST Data 44.1KHz FS corresponds to a 45 MBaud data stream. Since the Bigfoot transmitter is used as optical source, this is the link PWV/APWD which appears from node to node. Optical power data are average values when using a MOST optical transmitter with peak of 650 nm typical and measured at the end of a plastic optical fiber with metal insert. *3) Any receiving circuitry receiving data from RX_DATA must be powered within 50ms after /STATUS gets active. There must be a protective resistor of 50Ohm (minimum) between RX_DATA and the receiving circuitry. A typical value for this resistor is 150Ohm.
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 3
SPF MIR3 02
Mechanical Design MIR3 02: CAI package (cavity as interface)
Lot number, production week, component type are given on CAI backside by laser marking (for details see marking specification).
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 4
SPF MIR3 02
Application Circuit:
*1) Place these components as close as possible to their corresponding pins of the FOT. *2) Values can change due to different light output power of the LED. *3) This is just a proposal for the Rext application. There can be used also other circuits to switch Rext from 15K to 30K.
Design & Layout rules:
* The 100nF bypass capacitors of the FOTs must be located as close as possible between the pins VCC and GND of the FOTs. Use ceramic caps and tantalum caps with low ESR. * Also the inductor/ ferrite bead (receiver) and the -3dB - control circuit (transmitter) must be placed as close as possible to the FOTs. We prefer ferrite beads (e.g. type 74279214 Wurth Elektronik) since the D.C. resistance is very low. In case other inductors are used, the D.C. resistance should be less than 3Ohm. * For EMC, a ferrite bead should be connected to the power supply, close to the transmitter and the receiver. Do not use only one ferrite bead together for receiver and transmitter!
Preliminary Product Information 2-Dec-02 Infineon AG Oasis SiliconSystems AG CONFIDENTIAL Page 5
SPF MIR3 02 * For the ground connection a ground plane is recommended (Y-structure). That means the ground planes of the transmitter, the receiver and the shielding must be separated. The three ground planes should be connected together behind the bypass capacitors (refer to the PCB design below). This ground signal should be connected directly to the ground plane of the MOST controller (e.g. OS8104) and the power supply on the top layer and/or bottom layer and ground layer as it is indicated in the example below. * If a multi layer design is used the ground layer must have the same ground separation like shown for the top layer! * A serial resistor in the Rx/ Tx data line will also reduce EMC - problems. For Rx the resistor must be placed near the receiver - for Tx the resistor must be placed near the MOST controller chip. The value depends on the distance between the FOTs and the MOST chip (< 5cm) and can be within a range up to 150R. Higher values for the resistors will increase jitter and can therefore cause locking problems of the MOST PLL! * The Rx/ Tx signals should not be routed in parallel over a long distance, but may be embedded with ground copper, if possible. * The GND pin and the pin of Rext (15K - resistor) of the transmitter are used for heat dissipation. Therefore there should be a good connection to the PCB a no isolation gaps! Both pins should dip into a copper area (see layout example below).
Layout example:
The reference board from OASIS Silicon Systems follows the requirements above. The schematic is very similar to the example above, but does not include the connection to the power supply, the OS8104 or the micro controller.
The examples below for top- and bottom layer is the layout of the reference design board and shows how the layout around the optical receiver and transmitter should look like. It is strongly recommended to follow these examples in your design to get best performance! Note: The buffer circuit (IC1), the connectors and jumpers in the middle to the right section of the schematic are only for being used together with the reference board, and will not be necessary for your hardware design.
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 6
SPF MIR3 02 Top Layer with 180 version of the pigtail:
GND - BUS to OS8104 and Power Supply
Bottom Layer (seen from the top side of the PCB):
GND - BUS to OS8104 and Power Supply
Bottom Layer: Bottom side / positions
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 7
SPF MIR3 02 Other items: * The shown circuit for the -3dB attenuation is just a proposal. Also any other circuit which can double the value of Rext is permitted. * Due to the fact that the optical average level jumps if the power control signal (/-3dB) is toggled, LOCK/ coding - errors can occur at the subsequent device for a short time. This is not very critical, since it occurs only in diagnosis mode. After a time of 10ms, the device should lock again if the optical attenuation between the devices is not too high. * The Rx and Tx signals can be measured by using standard probes (>1M/<10pF). However, if the signal quality is very bad, and the LOCK signal of the MOST chip is flaky, connecting a passive probe to the Rx signal can cause the MOST chip to lock better or worse to the signal. This is due to the capacitance of the analog probe which is usually in the range of 8..12pF, which shifts the phase and PWD of the signal. In this case an active probe with a capacitance of less than 1pF is recommended. * The reference test board which corresponds to the layout examples above, is available at the Oasis SiliconSystems AG.
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 8
SPF MIR3 02
History of Design and Specification Status of MOST Receiver:
Data Sheet Status 2-Dec-02 Bigfoot IC Revision J device marking date code, MIR3 02 comments, cause of change, important differences to last Status New release
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 9
SPF MIR3 02
Notes:
Preliminary Product Information 2-Dec-02
Infineon AG Oasis SiliconSystems AG
CONFIDENTIAL Page 10

▲Up To Search▲

Price & Availability of SPFMIR302

	To Download SPFMIR302 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .